By Stephen Nellis
(Reuters) - Intel Corp (NASDAQ:INTC) on Wednesday introduced a new, faster family of processor chips for personal computers and said that the supercomputer it is helping the U.S. government to build will reach double previously expected speeds.
Intel is working to regain its lead in making the fastest computing chips after having lost its title to rivals such as Advanced Micro Devices (NASDAQ:AMD) and Apple Inc (NASDAQ:AAPL), both of which use outside partners to make their chips while Intel has struggled with its internal manufacturing operations. Santa Clara, California-based Intel made the announcement at an event aimed at persuading software developers to write code for its chips.
Intel showed versions of its 12th generation of Intel Core chips for PCs, known by their code name of Alder Lake. The company said the product line will eventually include 60 different chips destined for 500 models of PCs from various makers, from thin laptops to larger machines designed for gamers.
The company said it is shipping 28 versions of the chip to PC makers, with "broad availability" starting on Nov. 4.
Intel also said that Aurora, a supercomputer that Intel is building with the U.S. Department of Energy's Argonne National Laboratory (NYSE:LH) for artificial intelligence work in suburban Chicago, will be twice as fast as originally planned. Intel said the computer will exceed 2 exaflops, meaning the ability to perform 2 quintillion - or 2,000,000,000,000,000,000 - calculations per second.
Intel had originally committed https://www.reuters.com/article/ctech-us-usa-intel-idCAKCN1QZ298-OCATC to deliver the $500 million computer this year with 1 exaflop of performance, but manufacturing delays forced it to postpone delivery until next year. In the meantime, Argonne officials tapped Intel's rivals https://www.reuters.com/article/nvidia-amd-idCNL1N2PV1L6 Nvidia (NASDAQ:NVDA) Corp and AMD for a smaller system built by Hewlett Packard Enterprise (NYSE:HPE) Co as a test system to continue developing software technologies for the delayed machine.